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authorSami Kerola2011-05-31 20:31:25 +0200
committerKarel Zak2011-06-08 13:09:02 +0200
commitacfa47232f262ab8cfc6f0eb1363eeda3ed56b9d (patch)
tree71d3bf18f2af3b523427c1d41d85ccec204686bd /tests/expected/lscpu
parentcfdisk: fix gcc warning (unused variable) (diff)
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tests: add lscpu dumps from three Dell's & a Xen
x86_64-dell_poweredgeR610 Ubuntu 11.04 kernel 2.6.38-8 x86_64-dell_poweredge1950 Red Hat EL 4.5 kernel 2.6.9-55.ELsmp x86_64-dell_e4310 Red Hat EL 5.3 kernel 2.6.18-194.17.4.el5 x86_64-el5xen Red Hat EL 5.6 kernel 2.6.18-238.el5xen Signed-off-by: Sami Kerola <sami.kerola@tomtom.com>
Diffstat (limited to 'tests/expected/lscpu')
-rw-r--r--tests/expected/lscpu/lscpu-x86_64-dell_e431028
-rw-r--r--tests/expected/lscpu/lscpu-x86_64-dell_poweredge195023
-rw-r--r--tests/expected/lscpu/lscpu-x86_64-dell_poweredgeR61040
-rw-r--r--tests/expected/lscpu/lscpu-x86_64-el5xen30
4 files changed, 121 insertions, 0 deletions
diff --git a/tests/expected/lscpu/lscpu-x86_64-dell_e4310 b/tests/expected/lscpu/lscpu-x86_64-dell_e4310
new file mode 100644
index 000000000..7131e3efd
--- /dev/null
+++ b/tests/expected/lscpu/lscpu-x86_64-dell_e4310
@@ -0,0 +1,28 @@
+CPU op-mode(s): 32-bit, 64-bit
+CPU(s): 4
+On-line CPU(s) list: 0-3
+Thread(s) per core: 2
+Core(s) per socket: 2
+CPU socket(s): 1
+NUMA node(s): 1
+Vendor ID: GenuineIntel
+CPU family: 6
+Model: 37
+Stepping: 5
+CPU MHz: 1199.000
+BogoMIPS: 5319.97
+Virtualization: VT-x
+L1d cache: 32K
+L1i cache: 32K
+L2 cache: 256K
+L3 cache: 3072K
+NUMA node0 CPU(s): 0-3
+
+# The following is the parsable format, which can be fed to other
+# programs. Each different item in every column has an unique ID
+# starting from zero.
+# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
+0,0,0,0,,0,0,0,0
+1,1,0,0,,1,1,1,0
+2,0,0,0,,0,0,0,0
+3,1,0,0,,1,1,1,0
diff --git a/tests/expected/lscpu/lscpu-x86_64-dell_poweredge1950 b/tests/expected/lscpu/lscpu-x86_64-dell_poweredge1950
new file mode 100644
index 000000000..64c5a9cd0
--- /dev/null
+++ b/tests/expected/lscpu/lscpu-x86_64-dell_poweredge1950
@@ -0,0 +1,23 @@
+CPU op-mode(s): 32-bit, 64-bit
+CPU(s): 8
+NUMA node(s): 1
+Vendor ID: GenuineIntel
+CPU family: 6
+Model: 15
+Stepping: 7
+CPU MHz: 2327.526
+BogoMIPS: 4655.08
+NUMA node0 CPU(s): 0-7
+
+# The following is the parsable format, which can be fed to other
+# programs. Each different item in every column has an unique ID
+# starting from zero.
+# CPU,Core,Socket,Node
+0,,,0
+1,,,0
+2,,,0
+3,,,0
+4,,,0
+5,,,0
+6,,,0
+7,,,0
diff --git a/tests/expected/lscpu/lscpu-x86_64-dell_poweredgeR610 b/tests/expected/lscpu/lscpu-x86_64-dell_poweredgeR610
new file mode 100644
index 000000000..55791ce7d
--- /dev/null
+++ b/tests/expected/lscpu/lscpu-x86_64-dell_poweredgeR610
@@ -0,0 +1,40 @@
+CPU op-mode(s): 32-bit, 64-bit
+CPU(s): 16
+Thread(s) per core: 2
+Core(s) per socket: 4
+CPU socket(s): 2
+NUMA node(s): 2
+Vendor ID: GenuineIntel
+CPU family: 6
+Model: 26
+Stepping: 5
+CPU MHz: 2261.056
+BogoMIPS: 4522.04
+Virtualization: VT-x
+L1d cache: 32K
+L1i cache: 32K
+L2 cache: 256K
+L3 cache: 8192K
+NUMA node0 CPU(s): 0,2,4,6,8,10,12,14
+NUMA node1 CPU(s): 1,3,5,7,9,11,13,15
+
+# The following is the parsable format, which can be fed to other
+# programs. Each different item in every column has an unique ID
+# starting from zero.
+# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
+0,0,0,0,,0,0,0,0
+1,1,1,1,,1,1,1,1
+2,2,0,0,,2,2,2,0
+3,3,1,1,,3,3,3,1
+4,4,0,0,,4,4,4,0
+5,5,1,1,,5,5,5,1
+6,6,0,0,,6,6,6,0
+7,7,1,1,,7,7,7,1
+8,0,0,0,,0,0,0,0
+9,1,1,1,,1,1,1,1
+10,2,0,0,,2,2,2,0
+11,3,1,1,,3,3,3,1
+12,4,0,0,,4,4,4,0
+13,5,1,1,,5,5,5,1
+14,6,0,0,,6,6,6,0
+15,7,1,1,,7,7,7,1
diff --git a/tests/expected/lscpu/lscpu-x86_64-el5xen b/tests/expected/lscpu/lscpu-x86_64-el5xen
new file mode 100644
index 000000000..c801b2350
--- /dev/null
+++ b/tests/expected/lscpu/lscpu-x86_64-el5xen
@@ -0,0 +1,30 @@
+CPU op-mode(s): 32-bit, 64-bit
+CPU(s): 8
+Thread(s) per core: 1
+Core(s) per socket: 1
+CPU socket(s): 8
+Vendor ID: GenuineIntel
+CPU family: 6
+Model: 26
+Stepping: 5
+CPU MHz: 2393.998
+BogoMIPS: 5986.29
+Hypervisor vendor: Xen
+Virtualization type: para
+L1d cache: 32K
+L1i cache: 32K
+L2 cache: 256K
+L3 cache: 8192K
+
+# The following is the parsable format, which can be fed to other
+# programs. Each different item in every column has an unique ID
+# starting from zero.
+# CPU,Core,Socket,Node,,L1d,L1i,L2,L3
+0,0,0,,,0,0,0,0
+1,1,1,,,0,0,0,0
+2,2,2,,,1,1,1,0
+3,3,3,,,1,1,1,0
+4,4,4,,,2,2,2,0
+5,5,5,,,2,2,2,0
+6,6,6,,,3,3,3,0
+7,7,7,,,3,3,3,0