summaryrefslogblamecommitdiffstats
path: root/target/arm/a32-uncond.decode
blob: 2339de2e943309e9ebd276cc455c547a28bce09c (plain) (tree)
1
2
3
4
5
6
7
8






                                                               
                                                                    














                                                                              
 
                        
                            
                  





                                                                            




                          
                                  


                                                                      

                                                                            








                                                          


                                                                     









                                                                            







                                                                     
# A32 unconditional instructions
#
#  Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.

#
# This file is processed by scripts/decodetree.py
#
# All insns that have 0xf in insn[31:28] are decoded here.
# All of those that have a COND field in insn[31:28] are in a32.decode
#

&empty           !extern
&i               !extern imm
&setend          E

# Branch with Link and Exchange

%imm24h          0:s24 24:1 !function=times_2

BLX_i            1111 101 . ........................          &i imm=%imm24h

# System Instructions

&rfe             rn w pu
&srs             mode w pu
&cps             mode imod M A I F

RFE              1111 100 pu:2 0 w:1 1 rn:4 0000 1010 0000 0000   &rfe
SRS              1111 100 pu:2 1 w:1 0 1101 0000 0101 000 mode:5  &srs
CPS              1111 0001 0000 imod:2 M:1 0 0000 000 A:1 I:1 F:1 0 mode:5 \
                 &cps

# Clear-Exclusive, Barriers

# QEMU does not require the option field for the barriers.
CLREX            1111 0101 0111 1111 1111 0000 0001 1111
DSB              1111 0101 0111 1111 1111 0000 0100 ----
DMB              1111 0101 0111 1111 1111 0000 0101 ----
ISB              1111 0101 0111 1111 1111 0000 0110 ----
SB               1111 0101 0111 1111 1111 0000 0111 0000

# Set Endianness
SETEND           1111 0001 0000 0001 0000 00 E:1 0 0000 0000  &setend

# Preload instructions

PLD              1111 0101 -101 ---- 1111 ---- ---- ----    # (imm, lit) 5te
PLDW             1111 0101 -001 ---- 1111 ---- ---- ----    # (imm, lit) 7mp
PLI              1111 0100 -101 ---- 1111 ---- ---- ----    # (imm, lit) 7

PLD              1111 0111 -101 ---- 1111 ----- -- 0 ----   # (register) 5te
PLDW             1111 0111 -001 ---- 1111 ----- -- 0 ----   # (register) 7mp
PLI              1111 0110 -101 ---- 1111 ----- -- 0 ----   # (register) 7

# Unallocated memory hints
#
# Since these are v7MP nops, and PLDW is v7MP and implemented as nop,
# (ab)use the PLDW helper.

PLDW             1111 0100 -001 ---- ---- ---- ---- ----
PLDW             1111 0110 -001 ---- ---- ---- ---0 ----