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| author | Klaus Jensen | 2020-11-13 09:50:33 +0100 |
|---|---|---|
| committer | Klaus Jensen | 2021-02-08 21:15:53 +0100 |
| commit | 1901b4967c3fdd47e59d9023aea2285d94f3998a (patch) | |
| tree | 2a11540c20dd5662b2a0e167b91320bc42a04d21 /.travis.yml | |
| parent | hw/block/nvme: indicate CMB support through controller capabilities register (diff) | |
| download | qemu-1901b4967c3fdd47e59d9023aea2285d94f3998a.tar.gz qemu-1901b4967c3fdd47e59d9023aea2285d94f3998a.tar.xz qemu-1901b4967c3fdd47e59d9023aea2285d94f3998a.zip | |
hw/block/nvme: move msix table and pba to BAR 0
In the interest of supporting both CMB and PMR to be enabled on the same
device, move the MSI-X table and pending bit array out of BAR 4 and into
BAR 0.
This is a simplified version of the patch contributed by Andrzej
Jakowski (see [1]). Leaving the CMB at offset 0 removes the need for
changes to CMB address mapping code.
[1]: https://lore.kernel.org/qemu-devel/20200729220107.37758-3-andrzej.jakowski@linux.intel.com/
Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com>
Tested-by: Minwoo Im <minwoo.im.dev@gmail.com>
Reviewed-by: Keith Busch <kbusch@kernel.org>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions