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author | Eric Auger | 2020-07-28 17:08:15 +0200 |
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committer | Peter Maydell | 2020-08-24 11:02:06 +0200 |
commit | de206dfd80412ed1cdfb70d43ad53c59a19361ab (patch) | |
tree | 9701cb7a6c4ac5fbed439e55f455c4c3be68db9f /hw/arm/smmuv3-internal.h | |
parent | hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support (diff) | |
download | qemu-de206dfd80412ed1cdfb70d43ad53c59a19361ab.tar.gz qemu-de206dfd80412ed1cdfb70d43ad53c59a19361ab.tar.xz qemu-de206dfd80412ed1cdfb70d43ad53c59a19361ab.zip |
hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
Expose the RIL bit so that the guest driver uses range
invalidation. Although RIL is a 3.2 features, We let
the AIDR advertise SMMUv3.1 support as v3.x implementation
is allowed to implement features from v3.(x+1).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-12-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/smmuv3-internal.h')
-rw-r--r-- | hw/arm/smmuv3-internal.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h index 9ae7d97faf..fa3c088972 100644 --- a/hw/arm/smmuv3-internal.h +++ b/hw/arm/smmuv3-internal.h @@ -55,6 +55,7 @@ REG32(IDR1, 0x4) REG32(IDR2, 0x8) REG32(IDR3, 0xc) FIELD(IDR3, HAD, 2, 1); + FIELD(IDR3, RIL, 10, 1); REG32(IDR4, 0x10) REG32(IDR5, 0x14) FIELD(IDR5, OAS, 0, 3); |