diff options
| author | Rémi Denis-Courmont | 2020-11-02 17:52:16 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-11-02 17:52:16 +0100 |
| commit | 3f0b59070c89f2261ff5961980ff5203b0c6bea9 (patch) | |
| tree | 87b65a2ad33a95dd976b74a348f31db240d7b8f2 /hw/arm | |
| parent | hw/arm/smmuv3: Fix potential integer overflow (CID 1432363) (diff) | |
| download | qemu-3f0b59070c89f2261ff5961980ff5203b0c6bea9.tar.gz qemu-3f0b59070c89f2261ff5961980ff5203b0c6bea9.tar.xz qemu-3f0b59070c89f2261ff5961980ff5203b0c6bea9.zip | |
hw/arm/boot: fix SVE for EL3 direct kernel boot
When booting a CPU with EL3 using the -kernel flag, set up CPTR_EL3 so
that SVE will not trap to EL3.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201030151541.11976-1-remi@remlab.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/boot.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 3e9816af80..cf97600a91 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -742,6 +742,9 @@ static void do_cpu_reset(void *opaque) if (cpu_isar_feature(aa64_mte, cpu)) { env->cp15.scr_el3 |= SCR_ATA; } + if (cpu_isar_feature(aa64_sve, cpu)) { + env->cp15.cptr_el[3] |= CPTR_EZ; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: |