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| author | Bin Meng | 2020-09-03 12:40:18 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | 70eb9f9cd1c0b519b31df8ab08ee2198b0e16176 (patch) | |
| tree | edda50d2ae4666242c391c913f473118749e6919 /hw/char/sifive_uart.c | |
| parent | hw/riscv: Move sifive_plic model to hw/intc (diff) | |
| download | qemu-70eb9f9cd1c0b519b31df8ab08ee2198b0e16176.tar.gz qemu-70eb9f9cd1c0b519b31df8ab08ee2198b0e16176.tar.xz qemu-70eb9f9cd1c0b519b31df8ab08ee2198b0e16176.zip | |
hw/riscv: Move riscv_htif model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/char/sifive_uart.c')
0 files changed, 0 insertions, 0 deletions