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| author | Peter Maydell | 2017-01-20 12:15:10 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-01-20 12:15:10 +0100 |
| commit | b3b48f529fe8dad6c28bd25ec4a4a7ee7a0b0dcd (patch) | |
| tree | e681ad07cf7423eb56afacc54600b33951e7e51c /hw/intc/trace-events | |
| parent | hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers (diff) | |
| download | qemu-b3b48f529fe8dad6c28bd25ec4a4a7ee7a0b0dcd.tar.gz qemu-b3b48f529fe8dad6c28bd25ec4a4a7ee7a0b0dcd.tar.xz qemu-b3b48f529fe8dad6c28bd25ec4a4a7ee7a0b0dcd.zip | |
hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR
Implement the two remaining ICV_ registers: EOIR and IAR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1483977924-14522-12-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/trace-events')
| -rw-r--r-- | hw/intc/trace-events | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/intc/trace-events b/hw/intc/trace-events index fc9ec576a6..1dcc8306a5 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -136,6 +136,8 @@ gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR write cpu %x va gicv3_icv_rpr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_RPR read cpu %x value 0x%" PRIx64 gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d read cpu %x value 0x%" PRIx64 gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu %x value 0x%" PRIx64 +gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu %x value 0x%" PRIx64 +gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu %x value 0x%" PRIx64 # hw/intc/arm_gicv3_dist.c gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" |