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| author | Peter Maydell | 2017-01-20 12:15:10 +0100 |
|---|---|---|
| committer | Peter Maydell | 2017-01-20 12:15:10 +0100 |
| commit | c5fc89b36c0a167548ae7af40dc085707a7756d2 (patch) | |
| tree | c8f160dc777465298bc11b31335a37aaaa359abc /hw/intc/trace-events | |
| parent | hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR (diff) | |
| download | qemu-c5fc89b36c0a167548ae7af40dc085707a7756d2.tar.gz qemu-c5fc89b36c0a167548ae7af40dc085707a7756d2.tar.xz qemu-c5fc89b36c0a167548ae7af40dc085707a7756d2.zip | |
hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()
Implement the function which signals virtual interrupts to the
CPU as appropriate following CPU interface state changes.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1483977924-14522-13-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/trace-events')
| -rw-r--r-- | hw/intc/trace-events | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 1dcc8306a5..6116df5436 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -138,6 +138,8 @@ gicv3_icv_hppir_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_HPPIR%d rea gicv3_icv_dir_write(uint32_t cpu, uint64_t val) "GICv3 ICV_DIR write cpu %x value 0x%" PRIx64 gicv3_icv_iar_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IAR%d read cpu %x value 0x%" PRIx64 gicv3_icv_eoir_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_EOIR%d write cpu %x value 0x%" PRIx64 +gicv3_cpuif_virt_update(uint32_t cpuid, int idx) "GICv3 CPU i/f %x virt HPPI update LR index %d" +gicv3_cpuif_virt_set_irqs(uint32_t cpuid, int fiqlevel, int irqlevel, int maintlevel) "GICv3 CPU i/f %x virt HPPI update: setting FIQ %d IRQ %d maintenance-irq %d" # hw/intc/arm_gicv3_dist.c gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d" |