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| author | Alex Richardson | 2020-11-30 18:01:17 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:43 +0100 |
| commit | 529577457cbba9e429af629c46204f63e50fa832 (patch) | |
| tree | 0b64abe8cb934d740a544d8ae3735d6c17a1b950 /hw/intc | |
| parent | target/riscv: Fix the bug of HLVX/HLV/HSV (diff) | |
| download | qemu-529577457cbba9e429af629c46204f63e50fa832.tar.gz qemu-529577457cbba9e429af629c46204f63e50fa832.tar.xz qemu-529577457cbba9e429af629c46204f63e50fa832.zip | |
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
The TW and TSR fields should be bits 21 and 22 and not 30/29.
This was found while comparing QEMU behaviour against the sail formal
model (https://github.com/rems-project/sail-riscv/).
Signed-off-by: Alex Richardson <Alexander.Richardson@cl.cam.ac.uk>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20201130170117.71281-1-Alexander.Richardson@cl.cam.ac.uk
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc')
0 files changed, 0 insertions, 0 deletions