diff options
| author | Christoffer Dall | 2014-02-26 18:19:59 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-02-26 18:19:59 +0100 |
| commit | 6453fa998a11e133e673c0a613b88484a8231d1d (patch) | |
| tree | 5d1e2b66c8741415e50e6fe0ec26c6de525210d0 /hw/intc | |
| parent | target-arm: Load correct access bits from ARMv5 level 2 page table descriptors (diff) | |
| download | qemu-6453fa998a11e133e673c0a613b88484a8231d1d.tar.gz qemu-6453fa998a11e133e673c0a613b88484a8231d1d.tar.xz qemu-6453fa998a11e133e673c0a613b88484a8231d1d.zip | |
hw/intc/arm_gic: Fix GIC_SET_LEVEL
The GIC_SET_LEVEL macro unfortunately overwrote the entire level
bitmask instead of just or'ing on the necessary bits, causing active
level PPIs on a core to clear PPIs on other cores.
Cc: qemu-stable@nongnu.org
Reported-by: Rob Herring <rob.herring@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Message-id: 1393031030-8692-1-git-send-email-christoffer.dall@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/gic_internal.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 92a6f7a3ff..48a58d7890 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -40,7 +40,7 @@ #define GIC_SET_MODEL(irq) s->irq_state[irq].model = true #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false #define GIC_TEST_MODEL(irq) s->irq_state[irq].model -#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level = (cm) +#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level |= (cm) #define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm) #define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0) #define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true |