diff options
| author | Atish Patra | 2022-05-14 00:14:58 +0200 |
|---|---|---|
| committer | Alistair Francis | 2022-05-24 01:48:20 +0200 |
| commit | 77046729f943ce2055648e8339ddd688dd67dd83 (patch) | |
| tree | 2ca2a2686eabb24d1dff1451c510b9b62c72b7bb /hw/intc | |
| parent | target/riscv: rvv: Fix early exit condition for whole register load/store (diff) | |
| download | qemu-77046729f943ce2055648e8339ddd688dd67dd83.tar.gz qemu-77046729f943ce2055648e8339ddd688dd67dd83.tar.xz qemu-77046729f943ce2055648e8339ddd688dd67dd83.zip | |
hw/intc: Pass correct hartid while updating mtimecmp
timecmp update function should be invoked with hartid for which
timecmp is being updated. The following patch passes the incorrect
hartid to the update function.
Fixes: e2f01f3c2e13 ("hw/intc: Make RISC-V ACLINT mtime MMIO register writable")
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220513221458.1192933-1-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/riscv_aclint.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 0412edc982..e6bceceefd 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -233,7 +233,8 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr, continue; } riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), - i, env->timecmp); + mtimer->hartid_base + i, + env->timecmp); } return; } |