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| author | Peter Maydell | 2020-11-19 22:56:04 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-12-10 12:44:55 +0100 |
| commit | 99c7834fba4e5f204a82a1c456de2148b9595135 (patch) | |
| tree | 0bd04b6e704a1f0a0c9eab293eac7f03fb7449d9 /hw/intc | |
| parent | target/arm: Implement FPCXT_S fp system register (diff) | |
| download | qemu-99c7834fba4e5f204a82a1c456de2148b9595135.tar.gz qemu-99c7834fba4e5f204a82a1c456de2148b9595135.tar.xz qemu-99c7834fba4e5f204a82a1c456de2148b9595135.zip | |
hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
The FPDSCR register has a similar layout to the FPSCR. In v8.1M it
gains new fields FZ16 (if half-precision floating point is supported)
and LTPSIZE (always reads as 4). Update the reset value and the code
that handles writes to this register accordingly.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 9628ce876e..be3bc1f1f4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2068,7 +2068,14 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, break; case 0xf3c: /* FPDSCR */ if (cpu_isar_feature(aa32_vfp_simd, cpu)) { - value &= 0x07c00000; + uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK; + if (cpu_isar_feature(any_fp16, cpu)) { + mask |= FPCR_FZ16; + } + value &= mask; + if (cpu_isar_feature(aa32_lob, cpu)) { + value |= 4 << FPCR_LTPSIZE_SHIFT; + } cpu->env.v7m.fpdscr[attrs.secure] = value; } break; |