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| author | Mark Cave-Ayland | 2022-03-05 16:09:52 +0100 |
|---|---|---|
| committer | Mark Cave-Ayland | 2022-03-09 10:28:28 +0100 |
| commit | 6c7266987297cf12e1474c2d634575194096e3c8 (patch) | |
| tree | 199078891b57a4c56ac4a7a5d5990833875a9868 /hw/misc/trace-events | |
| parent | mos6522: use device_class_set_parent_reset() to propagate reset to parent (diff) | |
| download | qemu-6c7266987297cf12e1474c2d634575194096e3c8.tar.gz qemu-6c7266987297cf12e1474c2d634575194096e3c8.tar.xz qemu-6c7266987297cf12e1474c2d634575194096e3c8.zip | |
mos6522: add register names to register read/write trace events
This helps to follow how the guest is programming the mos6522 when debugging.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220305150957.5053-8-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'hw/misc/trace-events')
| -rw-r--r-- | hw/misc/trace-events | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/misc/trace-events b/hw/misc/trace-events index fb5a389780..bd52cfc110 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -95,8 +95,8 @@ imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08 mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d" mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRId64 " delta_next=0x%"PRId64 mos6522_set_sr_int(void) "set sr_int" -mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64 -mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x" +mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64 +mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x" # npcm7xx_clk.c npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 |