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| author | Bin Meng | 2020-09-03 12:40:20 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-09-10 00:54:19 +0200 |
| commit | a4b84608ba0eecce1d4858181457dc26582e6d28 (patch) | |
| tree | c657deeba29792d6cda5b76235810d8763cc2497 /hw/net/cadence_gem.c | |
| parent | hw/riscv: Move sifive_uart model to hw/char (diff) | |
| download | qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.tar.gz qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.tar.xz qemu-a4b84608ba0eecce1d4858181457dc26582e6d28.zip | |
hw/riscv: Move sifive_test model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_test model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/net/cadence_gem.c')
0 files changed, 0 insertions, 0 deletions