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author | Bin Meng | 2021-03-06 07:01:52 +0100 |
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committer | Alistair Francis | 2021-03-23 02:54:40 +0100 |
commit | aac8e46e9da6e6ad048d858ecb033c953753f31a (patch) | |
tree | 562f738512bf14ac408e2e73ea21368f2f528fe6 /hw/riscv/microchip_pfsoc.c | |
parent | target/riscv: Add proper two-stage lookup exception detection (diff) | |
download | qemu-aac8e46e9da6e6ad048d858ecb033c953753f31a.tar.gz qemu-aac8e46e9da6e6ad048d858ecb033c953753f31a.tar.xz qemu-aac8e46e9da6e6ad048d858ecb033c953753f31a.zip |
hw/block: m25p80: Support fast read for SST flashes
Per SST25VF016B datasheet [1], SST flash requires a dummy byte after
the address bytes. Note only SPI mode is supported by SST flashes.
[1] http://ww1.microchip.com/downloads/en/devicedoc/s71271_04.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210306060152.7250-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/microchip_pfsoc.c')
0 files changed, 0 insertions, 0 deletions