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| author | Alistair Francis | 2020-12-16 19:22:29 +0100 |
|---|---|---|
| committer | Alistair Francis | 2020-12-18 06:56:44 +0100 |
| commit | c0a635f3973d974befb954463287786fd988bb64 (patch) | |
| tree | b06eb031a496452bcd61e464ccb707dad2d82289 /hw/riscv/spike.c | |
| parent | hw/riscv: Expand the is 32-bit check to support more CPUs (diff) | |
| download | qemu-c0a635f3973d974befb954463287786fd988bb64.tar.gz qemu-c0a635f3973d974befb954463287786fd988bb64.tar.xz qemu-c0a635f3973d974befb954463287786fd988bb64.zip | |
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/spike.c')
0 files changed, 0 insertions, 0 deletions