summaryrefslogtreecommitdiffstats
path: root/hw/rtc
diff options
context:
space:
mode:
authorAnup Patel2022-06-16 05:15:43 +0200
committerAlistair Francis2022-07-03 02:03:20 +0200
commit435774992e82d2d16f025afbb20b4f7be9b242b0 (patch)
treee4a70542226b11f3a1a5604c3809e6aafc0100ff /hw/rtc
parenttarget/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits (diff)
downloadqemu-435774992e82d2d16f025afbb20b4f7be9b242b0.tar.gz
qemu-435774992e82d2d16f025afbb20b4f7be9b242b0.tar.xz
qemu-435774992e82d2d16f025afbb20b4f7be9b242b0.zip
target/riscv: Update default priority table for local interrupts
The latest AIA draft v0.3.0 defines a relatively simpler scheme for default priority assignments where: 1) local interrupts 24 to 31 and 48 to 63 are reserved for custom use and have implementation specific default priority. 2) remaining local interrupts 0 to 23 and 32 to 47 have a recommended (not mandatory) priority assignments. We update the default priority table and hviprio mapping as-per above. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220616031543.953776-3-apatel@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/rtc')
0 files changed, 0 insertions, 0 deletions