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| author | Peter Maydell | 2016-06-17 16:23:48 +0200 |
|---|---|---|
| committer | Peter Maydell | 2016-06-17 16:23:51 +0200 |
| commit | 227a8653669a8526dcef1020982628282f44820d (patch) | |
| tree | d9bd2ecaa4f7817f934e98056a7a770b35d6650a /include/exec | |
| parent | hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers (diff) | |
| download | qemu-227a8653669a8526dcef1020982628282f44820d.tar.gz qemu-227a8653669a8526dcef1020982628282f44820d.tar.xz qemu-227a8653669a8526dcef1020982628282f44820d.zip | |
hw/intc/arm_gicv3: Add IRQ handling CPU interface registers
Add the CPU interface registers which deal with acknowledging
and dismissing interrupts.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-19-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'include/exec')
0 files changed, 0 insertions, 0 deletions