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| author | Peter Maydell | 2021-05-04 14:09:11 +0200 |
|---|---|---|
| committer | Peter Maydell | 2021-05-10 18:21:54 +0200 |
| commit | 5bddf92e689c0a3da57f4fd17b83d4eb1e436b80 (patch) | |
| tree | b7c25948f690e9d2b97298874a22159167e156f0 /include/hw/misc | |
| parent | hw/misc/mps2-scc: Add "QEMU interface" comment (diff) | |
| download | qemu-5bddf92e689c0a3da57f4fd17b83d4eb1e436b80.tar.gz qemu-5bddf92e689c0a3da57f4fd17b83d4eb1e436b80.tar.xz qemu-5bddf92e689c0a3da57f4fd17b83d4eb1e436b80.zip | |
hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping
On some boards, SCC config register CFG0 bit 0 controls whether
parts of the board memory map are remapped. Support this with:
* a device property scc-cfg0 so the board can specify the
initial value of the CFG0 register
* an outbound GPIO line which tracks bit 0 and which the board
can wire up to provide the remapping
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20210504120912.23094-3-peter.maydell@linaro.org
Diffstat (limited to 'include/hw/misc')
| -rw-r--r-- | include/hw/misc/mps2-scc.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h index ea261ea30d..3b2d13ac9c 100644 --- a/include/hw/misc/mps2-scc.h +++ b/include/hw/misc/mps2-scc.h @@ -18,8 +18,14 @@ * + QOM property "scc-cfg4": value of the read-only CFG4 register * + QOM property "scc-aid": value of the read-only SCC_AID register * + QOM property "scc-id": value of the read-only SCC_ID register + * + QOM property "scc-cfg0": reset value of the CFG0 register * + QOM property array "oscclk": reset values of the OSCCLK registers * (which are accessed via the SYS_CFG channel provided by this device) + * + named GPIO output "remap": this tracks the value of CFG0 register + * bit 0. Boards where this bit controls memory remapping should + * connect this GPIO line to a function performing that mapping. + * Boards where bit 0 has no special function should leave the GPIO + * output disconnected. */ #ifndef MPS2_SCC_H #define MPS2_SCC_H @@ -55,6 +61,9 @@ struct MPS2SCC { uint32_t num_oscclk; uint32_t *oscclk; uint32_t *oscclk_reset; + uint32_t cfg0_reset; + + qemu_irq remap; }; #endif |