diff options
| author | Alistair Francis | 2020-10-14 02:17:25 +0200 |
|---|---|---|
| committer | Alistair Francis | 2020-10-22 21:00:22 +0200 |
| commit | 099be0358ee2cfb1cadf80d14297511215885219 (patch) | |
| tree | 5083e25bb530b6da2fbdbe382476414585ce4dd3 /include/hw/riscv | |
| parent | target/riscv: Fix implementation of HLVX.WU instruction (diff) | |
| download | qemu-099be0358ee2cfb1cadf80d14297511215885219.tar.gz qemu-099be0358ee2cfb1cadf80d14297511215885219.tar.xz qemu-099be0358ee2cfb1cadf80d14297511215885219.zip | |
hw/riscv: sifive_u: Allow specifying the CPU
Allow the user to specify the main application CPU for the sifive_u
machine.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Message-id: b8412086c8aea0eff30fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com
Diffstat (limited to 'include/hw/riscv')
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 22e7e6efa1..a9f7b4a084 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -48,6 +48,7 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; uint32_t serial; + char *cpu_type; } SiFiveUSoCState; #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") |