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| author | Xuzhou Cheng | 2021-03-03 14:52:51 +0100 |
|---|---|---|
| committer | Peter Maydell | 2021-03-10 14:54:51 +0100 |
| commit | 21bce3717e2cb70e3bea06e8684bae111c9f4dda (patch) | |
| tree | c517868aec6c460aa381385b310f84a56b5edfff /include/hw | |
| parent | hw/dma: Implement a Xilinx CSU DMA model (diff) | |
| download | qemu-21bce3717e2cb70e3bea06e8684bae111c9f4dda.tar.gz qemu-21bce3717e2cb70e3bea06e8684bae111c9f4dda.tar.xz qemu-21bce3717e2cb70e3bea06e8684bae111c9f4dda.zip | |
hw/arm: xlnx-zynqmp: Clean up coding convention issues
There are some coding convention warnings in xlnx-zynqmp.c and
xlnx-zynqmp.h, as reported by:
$ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h
$ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c
Let's clean them up.
Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20210303135254.3970-3-bmeng.cn@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'include/hw')
| -rw-r--r-- | include/hw/arm/xlnx-zynqmp.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 0678b419a2..c83ef23e92 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -60,7 +60,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) #define XLNX_ZYNQMP_GIC_REGIONS 6 -/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets +/* + * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets * and under-decodes the 64k region. This mirrors the 4k regions to every 4k * aligned address in the 64k region. To implement each GIC region needs a * number of memory region aliases. |