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authorPeter Maydell2022-08-12 19:41:56 +0200
committerPeter Maydell2022-09-29 18:35:05 +0200
commit042e85d14c0f7cf3adf9ce67dd45b311378e67fa (patch)
tree3afc417eba619d78e896bca3bf7adfc9f64ec22e /include
parenttarget/arm: Update SDCR_VALID_MASK to include SCCD (diff)
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target/arm: Rearrange cpu64.c so all the CPU initfns are together
cpu64.c has ended up in a slightly odd order -- it starts with the initfns for most of the models-real-hardware CPUs; after that comes a bunch of support code for SVE, SME, pauth and LPA2 properties. Then come the initfns for the 'host' and 'max' CPU types, and then after that one more models-real-hardware CPU initfn, for a64fx. (This ordering is partly historical and partly required because a64fx needs the SVE properties.) Reorder the file into: * CPU property support functions * initfns for real hardware CPUs * initfns for host and max * class boilerplate Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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