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| author | Peter Maydell | 2020-09-10 19:38:55 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-10-01 16:31:00 +0200 |
| commit | dfc523a84b06b6a4b583ed4c29d24fd980dd37a0 (patch) | |
| tree | d4bb85c260a672ec0aab19afb65868134981d8f0 /include | |
| parent | target/arm: Add ID register values for Cortex-M0 (diff) | |
| download | qemu-dfc523a84b06b6a4b583ed4c29d24fd980dd37a0.tar.gz qemu-dfc523a84b06b6a4b583ed4c29d24fd980dd37a0.tar.xz qemu-dfc523a84b06b6a4b583ed4c29d24fd980dd37a0.zip | |
target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
The M-profile definition of the MVFR1 ID register differs slightly
from the A-profile one, and in particular the check for "does the CPU
support fp16 arithmetic" is not the same.
We don't currently implement any M-profile CPUs with fp16 arithmetic,
so this is not yet a visible bug, but correcting the logic now
disarms this beartrap for when we eventually do.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions