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| author | Sai Pavan Boddu | 2020-02-24 10:39:24 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-28 17:14:57 +0100 |
| commit | 25f1d9f38bac040498814561714b794431af86c4 (patch) | |
| tree | 595b26e642a6e983467160b41dcb375fdf56a4af /linux-user | |
| parent | cpu/a9mpcore: Set number of GIC priority bits to 5 (diff) | |
| download | qemu-25f1d9f38bac040498814561714b794431af86c4.tar.gz qemu-25f1d9f38bac040498814561714b794431af86c4.tar.xz qemu-25f1d9f38bac040498814561714b794431af86c4.zip | |
cpu/arm11mpcore: Set number of GIC priority bits to 4
The GIC built into the ARM11MPCore is always implemented with 4
priority bits; set the GIC property accordingly.
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'linux-user')
0 files changed, 0 insertions, 0 deletions