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| author | Philippe Mathieu-Daudé | 2020-12-16 23:59:07 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé | 2021-01-14 17:13:53 +0100 |
| commit | 8b0ea9b638adadcf056f4a18fe53a7c6339beba8 (patch) | |
| tree | 25b77517bdd13f095f26af114b92b725f85c6b44 /linux-user | |
| parent | target/mips/mips-defs: Reorder CPU_MIPS5 definition (diff) | |
| download | qemu-8b0ea9b638adadcf056f4a18fe53a7c6339beba8.tar.gz qemu-8b0ea9b638adadcf056f4a18fe53a7c6339beba8.tar.xz qemu-8b0ea9b638adadcf056f4a18fe53a7c6339beba8.zip | |
target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1
'CPU_MIPS32' and 'CPU_MIPS64' definitions concern CPUs implementing
the "Release 1" ISA. Rename it with the 'R1' suffix, as the other
CPU definitions do.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210104221154.3127610-4-f4bug@amsat.org>
Diffstat (limited to 'linux-user')
0 files changed, 0 insertions, 0 deletions