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| author | Bin Meng | 2019-09-06 18:20:08 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:47 +0200 |
| commit | 0d95299468c8f19a306b93bb9b6940ea55945db5 (patch) | |
| tree | 15b4eaa6206b97d9f17b37aba661496b73b7df9f /scripts/modules/module_block.py | |
| parent | riscv: sifive_u: Update PLIC hart topology configuration string (diff) | |
| download | qemu-0d95299468c8f19a306b93bb9b6940ea55945db5.tar.gz qemu-0d95299468c8f19a306b93bb9b6940ea55945db5.tar.xz qemu-0d95299468c8f19a306b93bb9b6940ea55945db5.zip | |
riscv: sifive: Implement PRCI model for FU540
This adds a simple PRCI model for FU540 (sifive_u). It has different
register layout from the existing PRCI model for FE310 (sifive_e).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/modules/module_block.py')
0 files changed, 0 insertions, 0 deletions