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| author | Bin Meng | 2019-09-06 18:20:07 +0200 |
|---|---|---|
| committer | Palmer Dabbelt | 2019-09-17 17:42:47 +0200 |
| commit | ef965ce23956a9e5cde5c9e91081484ec68a4139 (patch) | |
| tree | 5014a028c3fdd96656e7be1a109e8f82b43dad7b /scripts/modules/module_block.py | |
| parent | riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC (diff) | |
| download | qemu-ef965ce23956a9e5cde5c9e91081484ec68a4139.tar.gz qemu-ef965ce23956a9e5cde5c9e91081484ec68a4139.tar.xz qemu-ef965ce23956a9e5cde5c9e91081484ec68a4139.zip | |
riscv: sifive_u: Update PLIC hart topology configuration string
With heterogeneous harts config, the PLIC hart topology configuration
string are "M,MS,.." because of the monitor hart #0.
Suggested-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'scripts/modules/module_block.py')
0 files changed, 0 insertions, 0 deletions