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| author | Michael Clark | 2018-03-02 13:31:13 +0100 |
|---|---|---|
| committer | Michael Clark | 2018-03-06 20:30:28 +0100 |
| commit | 04331d0b56a0cab2e40a39135a92a15266b37c36 (patch) | |
| tree | 20411fe7fe6cf2c5bd3f7098a67b4fb1a63fe3b9 /scripts/modules | |
| parent | SiFive RISC-V Test Finisher (diff) | |
| download | qemu-04331d0b56a0cab2e40a39135a92a15266b37c36.tar.gz qemu-04331d0b56a0cab2e40a39135a92a15266b37c36.tar.xz qemu-04331d0b56a0cab2e40a39135a92a15266b37c36.zip | |
RISC-V VirtIO Machine
RISC-V machine with device-tree, 16550a UART and VirtIO MMIO.
The following machine is implemented:
- 'virt'; CLINT, PLIC, 16550A UART, VirtIO MMIO, device-tree
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'scripts/modules')
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