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| author | Michael Clark | 2018-03-02 13:31:13 +0100 |
|---|---|---|
| committer | Michael Clark | 2018-03-06 20:30:28 +0100 |
| commit | 88a07990fa282e4b63845223e90d759ef6811264 (patch) | |
| tree | 3d121bfa1fed1621a26b69f9534d7353c1509e5e /scripts/modules | |
| parent | RISC-V Spike Machines (diff) | |
| download | qemu-88a07990fa282e4b63845223e90d759ef6811264.tar.gz qemu-88a07990fa282e4b63845223e90d759ef6811264.tar.xz qemu-88a07990fa282e4b63845223e90d759ef6811264.zip | |
SiFive RISC-V Test Finisher
Test finisher memory mapped device used to exit simulation.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Diffstat (limited to 'scripts/modules')
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