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| author | Peter Maydell | 2019-02-01 15:55:44 +0100 |
|---|---|---|
| committer | Peter Maydell | 2019-02-01 15:55:44 +0100 |
| commit | 4f61106614410945b1d1c93081544ad5b13044fc (patch) | |
| tree | 63f7cbd9211381fea1971911c025316361f83241 /scripts/switch-timer-api | |
| parent | target/arm/translate-a64: Don't underdecode SIMD ld/st single (diff) | |
| download | qemu-4f61106614410945b1d1c93081544ad5b13044fc.tar.gz qemu-4f61106614410945b1d1c93081544ad5b13044fc.tar.xz qemu-4f61106614410945b1d1c93081544ad5b13044fc.zip | |
target/arm/translate-a64: Don't underdecode add/sub extended register
In the "add/subtract (extended register)" encoding group, the "opt"
field in bits [23:22] must be zero. Correctly UNDEF the unallocated
encodings where this field is not zero.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190125182626.9221-6-peter.maydell@linaro.org
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions