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| author | Michael Clark | 2018-04-09 02:06:30 +0200 |
|---|---|---|
| committer | Michael Clark | 2018-05-06 00:39:38 +0200 |
| commit | e21659057066f2f4d42fa51a62ff07a23a632e40 (patch) | |
| tree | 15ec640e089979c2446e6ab6954fb5c3d087a461 /scripts/switch-timer-api | |
| parent | RISC-V: Clear mtval/stval on exceptions without info (diff) | |
| download | qemu-e21659057066f2f4d42fa51a62ff07a23a632e40.tar.gz qemu-e21659057066f2f4d42fa51a62ff07a23a632e40.tar.xz qemu-e21659057066f2f4d42fa51a62ff07a23a632e40.zip | |
RISC-V: Allow S-mode mxr access when priv ISA >= v1.10
The mstatus.MXR alias in sstatus should only be writable
by S-mode if the privileged ISA version >= v1.10. Also MXR
was masked in sstatus CSR read but not sstatus CSR writes.
Now we correctly mask sstatus.mxr in both read and write.
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/switch-timer-api')
0 files changed, 0 insertions, 0 deletions