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author | Peter Maydell | 2016-01-21 15:15:09 +0100 |
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committer | Peter Maydell | 2016-01-21 15:15:09 +0100 |
commit | 03fbf20f4da58f41998dc10ec7542f65d37ba759 (patch) | |
tree | 7fb7c5695aad485d9a3a3830177493afb9c704ee /target-arm/helper.c | |
parent | target-arm: ignore ELR_ELx[1] for exception return to 32-bit ARM mode (diff) | |
download | qemu-03fbf20f4da58f41998dc10ec7542f65d37ba759.tar.gz qemu-03fbf20f4da58f41998dc10ec7542f65d37ba759.tar.xz qemu-03fbf20f4da58f41998dc10ec7542f65d37ba759.zip |
target-arm: Implement FPEXC32_EL2 system register
The AArch64 FPEXC32_EL2 system register is visible at EL2 and EL3,
and allows those exception levels to read and write the FPEXC
register for a lower exception level that is using AArch32.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1453132414-8127-1-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper.c')
-rw-r--r-- | target-arm/helper.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 06eb7752c9..ae024869d0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2891,6 +2891,17 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, tlb_flush(CPU(cpu), 1); } +static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri) +{ + if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) { + return CP_ACCESS_TRAP_EL2; + } + if (env->cp15.cptr_el[3] & CPTR_TFP) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo v8_cp_reginfo[] = { /* Minimal set of EL0-visible registers. This will need to be expanded * significantly for system emulation of AArch64 CPUs. @@ -3151,6 +3162,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, .type = ARM_CP_NO_RAW, .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write }, + { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0, + .type = ARM_CP_ALIAS, + .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), + .access = PL2_RW, .accessfn = fpexc32_access }, REGINFO_SENTINEL }; |