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path: root/target-arm/helper.c
Commit message (Expand)AuthorAgeFilesLines
* Move target-* CPU file into a target/ folderThomas Huth2016-12-201-9623/+0Star
* Fix corruption of CPSR when SCTLR.EE is setJulian Brown2016-11-071-1/+1
* target-arm: Implement new HLT trap for semihostingPeter Maydell2016-10-241-2/+9
* target-arm: Add trace events for the generic timersPeter Maydell2016-10-171-4/+16
* target-arm: Implement dummy MDCCINT_EL1Peter Maydell2016-10-171-0/+8
* target-arm: Infrastucture changes to enable handling of tagged address loadin...Thomas Hanson2016-10-171-0/+46
* tcg: Merge GETPC and GETRARichard Henderson2016-09-161-3/+3
* arm: spelling fix: mismatchMichael Tokarev2016-09-131-1/+1
* target-arm: Add missed AArch32 TLBI sytem registersSergey Sorokin2016-07-141-0/+139
* softfloat: Implement run-time-configurable meaning of signaling NaN bitAleksandar Markovic2016-06-241-20/+20
* target-arm: Provide hook to tell GICv3 about changes of security statePeter Maydell2016-06-171-0/+2
* target-arm: Fix reset and migration of TTBCR(S)Peter Maydell2016-06-141-1/+4
* target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translationSergey Sorokin2016-06-061-16/+22
* target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64()Peter Maydell2016-06-061-3/+0Star
* target-arm: Add the HSTR_EL2 registerAlistair Francis2016-06-061-0/+7
* cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini2016-05-191-0/+1
* arm: move arm_log_exception into .c filePaolo Bonzini2016-05-191-0/+15
* target-arm: Avoid unnecessary TLB flush on TCR_EL2, TCR_EL3 writesPeter Maydell2016-05-121-4/+8
* target-arm: Fix descriptor address masking in ARM address translationSergey Sorokin2016-05-121-18/+11Star
* target-arm: Stage 2 permission fault was fixed in AArch32 stateSergey Sorokin2016-05-121-1/+3
* target-arm: Make the 64-bit version of VTCR do the migrationPeter Maydell2016-04-041-1/+5
* target-arm: Remove incorrect ALIAS tags from ESR_EL2 and ESR_EL3Peter Maydell2016-04-041-2/+0Star
* target-arm: Correctly reset SCTLR_EL3 for 64-bit CPUsPeter Maydell2016-04-041-10/+13
* target-arm: Fix translation level on early translation faultsSergey Sorokin2016-03-161-10/+12
* target-arm: implement SCTLR.EEPeter Crosthwaite2016-03-041-2/+21
* target-arm: implement SCTLR.B, drop bswap_codePaolo Bonzini2016-03-041-4/+4
* target-arm: Correct handling of writes to CPSR mode bits from gdb in usermodePeter Maydell2016-03-041-2/+9
* target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEFPeter Maydell2016-02-261-7/+121
* target-arm: Mark CNTHP_TVAL_EL2 as ARM_CP_NO_RAWEdgar E. Iglesias2016-02-261-1/+1
* target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM trapsPeter Maydell2016-02-261-7/+36
* target-arm: Fix handling of SDCR for 32-bit codePeter Maydell2016-02-261-8/+15
* target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1Peter Maydell2016-02-261-0/+10
* target-arm: Make mode switches from Hyp via CPS and MRS illegalPeter Maydell2016-02-261-2/+10
* target-arm: In v8, make illegal AArch32 mode changes set PSTATE.ILPeter Maydell2016-02-261-3/+12
* target-arm: Forbid mode switch to Mon from Secure EL1Peter Maydell2016-02-261-1/+1
* target-arm: Add Hyp mode checks to bad_mode_switch()Peter Maydell2016-02-261-0/+3
* target-arm: Add comment about not implementing NSACR.RFRPeter Maydell2016-02-261-0/+3
* target-arm: In cpsr_write() ignore mode switches from User modePeter Maydell2016-02-261-0/+1
* target-arm: Raw CPSR writes should skip checks and bank switchingPeter Maydell2016-02-261-2/+3
* target-arm: Add write_type argument to cpsr_write()Peter Maydell2016-02-261-1/+2
* target-arm: Add PMUSERENR_EL0 registerAlistair Francis2016-02-181-0/+6
* target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registersAlistair Francis2016-02-181-0/+12
* target-arm: Add the pmceid0 and pmceid1 registersAlistair Francis2016-02-181-0/+16
* target-arm: Move bank_number() into internals.hPeter Maydell2016-02-181-25/+0Star
* target-arm: Move get/set_r13_banked() to op_helper.cPeter Maydell2016-02-181-33/+0Star
* target-arm: Report correct syndrome for FPEXC32_EL2 trapsPeter Maydell2016-02-181-2/+2
* target-arm: Implement MDCR_EL3.TDA and MDCR_EL2.TDA trapsPeter Maydell2016-02-181-9/+30
* target-arm: Implement MDCR_EL2.TDRA trapsPeter Maydell2016-02-181-3/+24
* target-arm: Implement MDCR_EL3.TDOSA and MDCR_EL2.TDOSA trapsPeter Maydell2016-02-181-1/+22
* target-arm: correct CNTFRQ access rightsPeter Maydell2016-02-181-3/+26
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