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| author | Peter Maydell | 2014-09-12 15:06:49 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-09-12 15:06:49 +0200 |
| commit | 3ff6fc9148d0a9e683eb6ec78523a017247e990d (patch) | |
| tree | 1ecd027945386aebdf12a1e61e53f722528f193c /target-arm/helper.c | |
| parent | target-arm: Move extended_addresses_enabled() to internals.h (diff) | |
| download | qemu-3ff6fc9148d0a9e683eb6ec78523a017247e990d.tar.gz qemu-3ff6fc9148d0a9e683eb6ec78523a017247e990d.tar.xz qemu-3ff6fc9148d0a9e683eb6ec78523a017247e990d.zip | |
target-arm: Implement handling of fired watchpoints
Implement the ARM debug exception handler for dealing with
fired watchpoints.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 5fd5497a35..b0d2424df3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2399,14 +2399,18 @@ static void define_debug_regs(ARMCPU *cpu) * These are just dummy implementations for now. */ int i; - int wrps, brps; + int wrps, brps, ctx_cmps; ARMCPRegInfo dbgdidr = { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr, }; + /* Note that all these register fields hold "number of Xs minus 1". */ brps = extract32(cpu->dbgdidr, 24, 4); wrps = extract32(cpu->dbgdidr, 28, 4); + ctx_cmps = extract32(cpu->dbgdidr, 20, 4); + + assert(ctx_cmps <= brps); /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties * of the debug registers such as number of breakpoints; @@ -2415,6 +2419,7 @@ static void define_debug_regs(ARMCPU *cpu) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps); assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps); + assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps); } define_one_arm_cp_reg(cpu, &dbgdidr); |