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| author | Peter Maydell | 2014-12-11 13:07:49 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-12-11 13:07:49 +0100 |
| commit | 51a79b039728277e35fd19f7a7b4bc6cb323697f (patch) | |
| tree | 6e00fee2b4cb14e5a1f0ce99b6f770211b0eec33 /target-arm/helper.c | |
| parent | target-arm: add CPREG secure state support (diff) | |
| download | qemu-51a79b039728277e35fd19f7a7b4bc6cb323697f.tar.gz qemu-51a79b039728277e35fd19f7a7b4bc6cb323697f.tar.xz qemu-51a79b039728277e35fd19f7a7b4bc6cb323697f.zip | |
target-arm: add secure state bit to CPREG hash
Added additional NS-bit to CPREG hash encoding. Updated hash lookup
locations to specify hash bit currently set to non-secure.
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-7-git-send-email-greg.bellows@linaro.org
[PMM: fix uses of ENCODE_CP_REG in kvm32.c to add extra argument]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index a4483d8be5..5fc82038ec 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3287,7 +3287,7 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) } static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, int state, + void *opaque, int state, int secstate, int crm, int opc1, int opc2) { /* Private utility function for define_one_arm_cp_reg_with_opaque(): @@ -3296,6 +3296,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, uint32_t *key = g_new(uint32_t, 1); ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; + int ns = (r->secure & ARM_CP_SECSTATE_NS) ? 1 : 0; if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) { /* The AArch32 view of a shared register sees the lower 32 bits * of a 64 bit backing field. It is not migratable as the AArch64 @@ -3327,7 +3328,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, r2->opc0, opc1, opc2); } else { - *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2); + *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); } if (opaque) { r2->opaque = opaque; @@ -3477,7 +3478,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, continue; } add_cpreg_to_hashtable(cpu, r, opaque, state, - crm, opc1, opc2); + ARM_CP_SECSTATE_NS, crm, opc1, opc2); } } } |