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authorSergey Fedorov2015-04-26 17:49:25 +0200
committerPeter Maydell2015-04-26 17:49:25 +0200
commit7ebd5f2e03a00889619bb97e83062d27066d4a26 (patch)
tree52580739f4c9e678966c0c96b3b5c68a38a2e57e /target-arm/helper.c
parenttarget-arm: Check watchpoints against CPU security state (diff)
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target-arm: rename c1_coproc to cpacr_el1
Rename the field holding CPACR_EL1 system register state in AArch64 naming style. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> [PMM: also fixed a couple of missed occurrences in cpu.c] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
-rw-r--r--target-arm/helper.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 50469cdae0..0ac6ff15fb 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -589,7 +589,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
value &= mask;
}
- env->cp15.c1_coproc = value;
+ env->cp15.cpacr_el1 = value;
}
static const ARMCPRegInfo v6_cp_reginfo[] = {
@@ -615,7 +615,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
+ .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
.resetvalue = 0, .writefn = cpacr_write },
REGINFO_SENTINEL
};