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| author | Peter Maydell | 2015-08-25 16:45:07 +0200 |
|---|---|---|
| committer | Peter Maydell | 2015-08-25 16:45:07 +0200 |
| commit | 834a6c6920316d39aaf0e68ac936c0a3ad164815 (patch) | |
| tree | 716fa876a9ac89f45b3c973e7119b3d2e63962d1 /target-arm/helper.c | |
| parent | target-arm: Implement missing AFSR registers (diff) | |
| download | qemu-834a6c6920316d39aaf0e68ac936c0a3ad164815.tar.gz qemu-834a6c6920316d39aaf0e68ac936c0a3ad164815.tar.xz qemu-834a6c6920316d39aaf0e68ac936c0a3ad164815.zip | |
target-arm: Implement missing ACTLR registers
We already implemented ACTLR_EL1; add the missing ACTLR_EL2 and
ACTLR_EL3, for consistency.
Since we don't currently have any CPUs that need the EL2/EL3
versions to reset to non-zero values, implement as RAZ/WI.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1438281398-18746-5-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 21 |
1 files changed, 15 insertions, 6 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index f6119be888..97ca86ad0a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3936,13 +3936,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_AUXCR)) { - ARMCPRegInfo auxcr = { - .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, - .access = PL1_RW, .type = ARM_CP_CONST, - .resetvalue = cpu->reset_auxcr + ARMCPRegInfo auxcr_reginfo[] = { + { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST, + .resetvalue = cpu->reset_auxcr }, + { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL2_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1, + .access = PL3_RW, .type = ARM_CP_CONST, + .resetvalue = 0 }, + REGINFO_SENTINEL }; - define_one_arm_cp_reg(cpu, &auxcr); + define_arm_cp_regs(cpu, auxcr_reginfo); } if (arm_feature(env, ARM_FEATURE_CBAR)) { |