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| author | Edgar E. Iglesias | 2014-09-29 19:48:49 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-09-29 19:48:49 +0200 |
| commit | 9e729b57ac2a3adebee2746a2106a70eb8230a72 (patch) | |
| tree | 40c42b07039d287afba28b9fab38d784f69344fe /target-arm/helper.c | |
| parent | target-arm: Add SCR_EL3 (diff) | |
| download | qemu-9e729b57ac2a3adebee2746a2106a70eb8230a72.tar.gz qemu-9e729b57ac2a3adebee2746a2106a70eb8230a72.tar.xz qemu-9e729b57ac2a3adebee2746a2106a70eb8230a72.zip | |
target-arm: A64: Refactor aarch64_cpu_do_interrupt
Introduce new_el and new_mode in preparation for future patches
that add support for taking exceptions to and from EL2 and 3.
No functional change.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1411718914-6608-4-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index e47e7b4fdd..25477bd8af 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3704,6 +3704,11 @@ uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode) return 0; } +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) +{ + return 1; +} + #else /* Map CPU modes onto saved register banks. */ @@ -3759,6 +3764,14 @@ void switch_mode(CPUARMState *env, int mode) env->spsr = env->banked_spsr[i]; } +/* + * Determine the target EL for a given exception type. + */ +unsigned int arm_excp_target_el(CPUState *cs, unsigned int excp_idx) +{ + return 1; +} + static void v7m_push(CPUARMState *env, uint32_t val) { CPUState *cs = CPU(arm_env_get_cpu(env)); |