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| author | Peter Maydell | 2014-04-15 20:18:44 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-04-17 22:34:04 +0200 |
| commit | a50c0f51339ed1df0a2e289513e3e2bf5b5ca45c (patch) | |
| tree | 21ccde90de2f8ff2c25e6c3fd617da9233b9ca88 /target-arm/helper.c | |
| parent | target-arm: Implement AArch64 EL1 exception handling (diff) | |
| download | qemu-a50c0f51339ed1df0a2e289513e3e2bf5b5ca45c.tar.gz qemu-a50c0f51339ed1df0a2e289513e3e2bf5b5ca45c.tar.xz qemu-a50c0f51339ed1df0a2e289513e3e2bf5b5ca45c.zip | |
target-arm: Implement ARMv8 MVFR registers
For ARMv8 there are two changes to the MVFR media feature registers:
* there is a new MVFR2 which is accessible from 32 bit code
* 64 bit code accesses these via the usual sysreg instructions
rather than with a floating-point specific instruction
Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index e9b64f364a..cf5fab85a5 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2155,6 +2155,18 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->id_aa64mmfr1 }, + { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0, + .access = PL1_R, .type = ARM_CP_CONST, + .resetvalue = cpu->mvfr0 }, + { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1, + .access = PL1_R, .type = ARM_CP_CONST, + .resetvalue = cpu->mvfr1 }, + { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, + .access = PL1_R, .type = ARM_CP_CONST, + .resetvalue = cpu->mvfr2 }, REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v8_idregs); |