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| author | Peter Maydell | 2014-04-15 20:18:37 +0200 |
|---|---|---|
| committer | Peter Maydell | 2014-04-17 22:34:03 +0200 |
| commit | c2b820fe587b18448967cdd6d408abd1dc0471f2 (patch) | |
| tree | c20830b5786b1289ce979c8d5935aeb23ee360c4 /target-arm/helper.c | |
| parent | target-arm: Split out private-to-target functions into internals.h (diff) | |
| download | qemu-c2b820fe587b18448967cdd6d408abd1dc0471f2.tar.gz qemu-c2b820fe587b18448967cdd6d408abd1dc0471f2.tar.xz qemu-c2b820fe587b18448967cdd6d408abd1dc0471f2.zip | |
target-arm: Implement AArch64 DAIF system register
Implement the DAIF system register which is a view of the
DAIF bits in PSTATE. To avoid needing a readfn, we widen
the daif field in CPUARMState to uint64_t.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index e642b30170..c8348dabde 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1691,6 +1691,20 @@ static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri, vfp_set_fpsr(env, value); } +static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri) +{ + if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) { + return CP_ACCESS_TRAP; + } + return CP_ACCESS_OK; +} + +static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->daif = value & PSTATE_DAIF; +} + static CPAccessResult aa64_cacheop_access(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -1737,6 +1751,12 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "NZCV", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2, .access = PL0_RW, .type = ARM_CP_NZCV }, + { .name = "DAIF", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2, + .type = ARM_CP_NO_MIGRATE, + .access = PL0_RW, .accessfn = aa64_daif_access, + .fieldoffset = offsetof(CPUARMState, daif), + .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore }, { .name = "FPCR", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4, .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write }, |