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| author | Peter Maydell | 2016-02-11 12:17:30 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-02-11 12:17:30 +0100 |
| commit | efe4a274083f61484a8f1478d93f229d43aa8095 (patch) | |
| tree | 4612133d509af592c4ade854b242d2eb3ec31281 /target-arm/helper.c | |
| parent | target-arm: Implement MDCR_EL3 and SDCR (diff) | |
| download | qemu-efe4a274083f61484a8f1478d93f229d43aa8095.tar.gz qemu-efe4a274083f61484a8f1478d93f229d43aa8095.tar.xz qemu-efe4a274083f61484a8f1478d93f229d43aa8095.zip | |
target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR
The registers MVBAR and SCR should have the behaviour of trapping to
EL3 if accessed from Secure EL1, but we were incorrectly implementing
them to UNDEF (which would trap to EL1). Fix this by using the new
access_trap_aa32s_el1() access function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1454506721-11843-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 1efe304532..98eccd621c 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3548,7 +3548,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .resetvalue = 0, .writefn = scr_write }, { .name = "SCR", .type = ARM_CP_ALIAS, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, - .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), + .access = PL1_RW, .accessfn = access_trap_aa32s_el1, + .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), .writefn = scr_write }, { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1, @@ -3571,7 +3572,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { .access = PL3_W | PL1_R, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.nsacr) }, { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0, + .access = PL1_RW, .accessfn = access_trap_aa32s_el1, + .writefn = vbar_write, .resetvalue = 0, .fieldoffset = offsetof(CPUARMState, cp15.mvbar) }, { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64, .type = ARM_CP_ALIAS, /* reset handled by AArch32 view */ |