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| author | Peter Maydell | 2016-02-23 16:36:43 +0100 |
|---|---|---|
| committer | Peter Maydell | 2016-02-26 16:09:41 +0100 |
| commit | f8c88bbcda76d5674e4bb125471371b41d330df8 (patch) | |
| tree | 94a6ea0437de3b0629eba23dd6dde4e0e38a743c /target-arm/helper.c | |
| parent | target-arm: Add write_type argument to cpsr_write() (diff) | |
| download | qemu-f8c88bbcda76d5674e4bb125471371b41d330df8.tar.gz qemu-f8c88bbcda76d5674e4bb125471371b41d330df8.tar.xz qemu-f8c88bbcda76d5674e4bb125471371b41d330df8.zip | |
target-arm: Raw CPSR writes should skip checks and bank switching
Raw CPSR writes should skip the architectural checks for whether
we're allowed to set the A or F bits and should also not do
the switching of register banks if the mode changes. Handle
this inside cpsr_write(), which allows us to drop the "manually
set the mode bits to avoid the bank switch" code from all the
callsites which are using CPSRWriteRaw.
This fixes a bug in 32-bit KVM handling where we had forgotten
the "manually set the mode bits" part and could thus potentially
trash the register state if the mode from the last exit to userspace
differed from the mode on this exit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-4-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/helper.c')
| -rw-r--r-- | target-arm/helper.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 014bb80d85..c491cd80ab 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5268,7 +5268,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, * In a V8 implementation, it is permitted for privileged software to * change the CPSR A/F bits regardless of the SCR.AW/FW bits. */ - if (!arm_feature(env, ARM_FEATURE_V8) && + if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) && arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2) && !arm_is_secure(env)) { @@ -5315,7 +5315,8 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, env->daif &= ~(CPSR_AIF & mask); env->daif |= val & CPSR_AIF & mask; - if ((env->uncached_cpsr ^ val) & mask & CPSR_M) { + if (write_type != CPSRWriteRaw && + ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { if (bad_mode_switch(env, val & CPSR_M)) { /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. * We choose to ignore the attempt and leave the CPSR M field |