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| author | Peter Maydell | 2014-02-26 18:20:05 +0100 |
|---|---|---|
| committer | Peter Maydell | 2014-02-26 18:20:05 +0100 |
| commit | d9ea7d290b685844d3603103bc53ad977e6f68a3 (patch) | |
| tree | 382f70d418c5581facafbaa89521d04d976311e5 /target-arm/translate-a64.c | |
| parent | target-arm: Implement AArch64 OSLAR_EL1 sysreg as WI (diff) | |
| download | qemu-d9ea7d290b685844d3603103bc53ad977e6f68a3.tar.gz qemu-d9ea7d290b685844d3603103bc53ad977e6f68a3.tar.xz qemu-d9ea7d290b685844d3603103bc53ad977e6f68a3.zip | |
target-arm: Get MMU index information correct for A64 code
Emit the correct MMU index information for loads and stores from
A64 code, rather than hardwiring it to "always kernel mode",
by storing the exception level in the TB flags, and make
cpu_mmu_index() return the right answer when the CPU is in
AArch64 mode.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index ec2d9dc219..a6c8fabb61 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -9013,7 +9013,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, dc->condexec_mask = 0; dc->condexec_cond = 0; #if !defined(CONFIG_USER_ONLY) - dc->user = 0; + dc->user = (ARM_TBFLAG_AA64_EL(tb->flags) == 0); #endif dc->vfp_enabled = 0; dc->vec_len = 0; |