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| author | Peter Maydell | 2012-06-20 13:57:06 +0200 |
|---|---|---|
| committer | Peter Maydell | 2012-06-20 14:00:58 +0200 |
| commit | 200bf596b96820186883953de9bda26cac8e6bd7 (patch) | |
| tree | 0e986dae7195c711f1a327ed4f3e2f72d1621834 /target-arm | |
| parent | Allow machines to configure the QEMU_VERSION that's exposed via hardware (diff) | |
| download | qemu-200bf596b96820186883953de9bda26cac8e6bd7.tar.gz qemu-200bf596b96820186883953de9bda26cac8e6bd7.tar.xz qemu-200bf596b96820186883953de9bda26cac8e6bd7.zip | |
target-arm: Fix 11MPCore cache type register value
Make the 11MPCore report a valid value in its cache type register
(the previous value appears to have been incorrectly copied from
the 1136/1176). In particular, do not report that we have an
aliasing VIPT cache, because this causes Linux to attempt to use
the v6 block cache ops which the 11MPCore doesn't actually have.
(This causes no problems currently because we over-broadly provide
those ops on all cores, but prevents us correctly narrowing the
block ops down to those cores which actually implement them.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7eb323ae4d..934894bf93 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -307,7 +307,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->reset_fpsid = 0x410120b4; cpu->mvfr0 = 0x11111111; cpu->mvfr1 = 0x00000000; - cpu->ctr = 0x1dd20d2; + cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */ cpu->id_pfr0 = 0x111; cpu->id_pfr1 = 0x1; cpu->id_dfr0 = 0; |