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| author | Alistair Francis | 2015-05-29 08:31:58 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias | 2015-06-21 09:20:15 +0200 |
| commit | 4e5d45ae5756123b3b7000c8b0b3d3a9ea4737da (patch) | |
| tree | 9fe391902dfb3df058f1d695216030445f6b7d21 /target-microblaze | |
| parent | target-microblaze: Tidy up the base-vectors property (diff) | |
| download | qemu-4e5d45ae5756123b3b7000c8b0b3d3a9ea4737da.tar.gz qemu-4e5d45ae5756123b3b7000c8b0b3d3a9ea4737da.tar.xz qemu-4e5d45ae5756123b3b7000c8b0b3d3a9ea4737da.zip | |
target-microblaze: Convert use-fpu to a CPU property
Originally the use-fpu PVR bits were manually set for each machine. This
is a hassle and difficult to read, instead set them based on the CPU
properties.
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target-microblaze')
| -rw-r--r-- | target-microblaze/cpu-qom.h | 1 | ||||
| -rw-r--r-- | target-microblaze/cpu.c | 13 | ||||
| -rw-r--r-- | target-microblaze/translate.c | 10 |
3 files changed, 14 insertions, 10 deletions
diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index dd04199096..a6474f9124 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -63,6 +63,7 @@ typedef struct MicroBlazeCPU { struct { bool stackprot; uint32_t base_vectors; + uint8_t usefpu; } cfg; CPUMBState env; diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 0f805d334f..b857056a33 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -110,12 +110,14 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_USE_DIV_MASK \ | PVR2_USE_HW_MUL_MASK \ | PVR2_USE_MUL64_MASK \ - | PVR2_USE_FPU_MASK \ - | PVR2_USE_FPU2_MASK \ | PVR2_FPU_EXC_MASK \ | 0; - env->pvr.regs[0] |= cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0; + env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | + (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0); + + env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | + (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); @@ -161,6 +163,11 @@ static Property mb_properties[] = { DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, true), + /* If use-fpu > 0 - FPU is enabled + * If use-fpu = 2 - Floating point conversion and square root instructions + * are enabled + */ + DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index bd10b40000..8187700ba2 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1411,15 +1411,11 @@ static void dec_rts(DisasContext *dc) static int dec_check_fpuv2(DisasContext *dc) { - int r; - - r = dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU2_MASK; - - if (!r && (dc->tb_flags & MSR_EE_FLAG)) { + if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU); t_gen_raise_exception(dc, EXCP_HW_EXCP); } - return r; + return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK; } static void dec_fpu(DisasContext *dc) @@ -1428,7 +1424,7 @@ static void dec_fpu(DisasContext *dc) if ((dc->tb_flags & MSR_EE_FLAG) && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK) - && !((dc->cpu->env.pvr.regs[2] & PVR2_USE_FPU_MASK))) { + && (dc->cpu->cfg.usefpu != 1)) { tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); return; |