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authorMaciej W. Rozycki2014-11-03 19:51:38 +0100
committerLeon Alrae2014-12-16 13:45:19 +0100
commitc7d4d98ae7057467f48c02a11ad9120021976089 (patch)
tree9a85dc1a1da5395240ebfb34ec9a3a6b9c4e4f1e /target-mips
parenttarget-mips: Correct the handling of register #72 on writes (diff)
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target-mips: Make CP1.FIR read-only here too
CP1.FIR is read-only in hardware so gdbstub must respect it. We already respect it for CTC1 instructions, so do it here too. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'target-mips')
-rw-r--r--target-mips/gdbstub.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index 7e3a604afa..e86df0e57c 100644
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -105,7 +105,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
RESTORE_ROUNDING_MODE;
break;
case 71:
- env->active_fpu.fcr0 = tmp;
+ /* FIR is read-only. Ignore writes. */
break;
}
return sizeof(target_ulong);