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| author | Richard Henderson | 2020-06-26 05:31:31 +0200 |
|---|---|---|
| committer | Peter Maydell | 2020-06-26 15:31:12 +0200 |
| commit | 206adacfb8d35e671e3619591608c475aa046b63 (patch) | |
| tree | 44ed93ca28ab3c527316dc4fcc1d680bd3600b63 /target/arm/cpu.h | |
| parent | target/arm: Add arm_tlb_bti_gp (diff) | |
| download | qemu-206adacfb8d35e671e3619591608c475aa046b63.tar.gz qemu-206adacfb8d35e671e3619591608c475aa046b63.tar.xz qemu-206adacfb8d35e671e3619591608c475aa046b63.zip | |
target/arm: Add mte helpers for sve scalar + int loads
Because the elements are sequential, we can eliminate many tests all
at once when the tag hits TCMA, or if the page(s) are not Tagged.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200626033144.790098-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c54f0ab18a..3bf0518ca4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3405,6 +3405,7 @@ static inline MemTxAttrs *typecheck_memtxattrs(MemTxAttrs *x) * generic target bits directly. */ #define arm_tlb_bti_gp(x) (typecheck_memtxattrs(x)->target_tlb_bit0) +#define arm_tlb_mte_tagged(x) (typecheck_memtxattrs(x)->target_tlb_bit1) /* * Naming convention for isar_feature functions: |