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| author | Peter Maydell | 2020-02-24 18:28:45 +0100 |
|---|---|---|
| committer | Peter Maydell | 2020-02-28 17:14:57 +0100 |
| commit | 2677cf9f92a5319bb995927f9225940414ce879d (patch) | |
| tree | 33052fe3e31a742b3510f32e25693d2d645b48c2 /target/arm/cpu.h | |
| parent | target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 (diff) | |
| download | qemu-2677cf9f92a5319bb995927f9225940414ce879d.tar.gz qemu-2677cf9f92a5319bb995927f9225940414ce879d.tar.xz qemu-2677cf9f92a5319bb995927f9225940414ce879d.zip | |
target/arm: Implement v8.3-RCPC
The v8.3-RCPC extension implements three new load instructions
which provide slightly weaker consistency guarantees than the
existing load-acquire operations. For QEMU we choose to simply
implement them with a full LDAQ barrier.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200224172846.13053-3-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6013287f62..ff30985ead 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3774,6 +3774,11 @@ static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } +static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ |