summaryrefslogtreecommitdiffstats
path: root/target/arm/cpu.h
diff options
context:
space:
mode:
authorRichard Henderson2019-03-01 21:04:59 +0100
committerPeter Maydell2019-03-05 16:55:08 +0100
commit5ef84f111483e3f7b57efc690e22081ca8f99544 (patch)
tree622e6e3081b2959bb9fe5975f309bed8594b2a17 /target/arm/cpu.h
parenttarget/arm: Implement ARMv8.4-CondM (diff)
downloadqemu-5ef84f111483e3f7b57efc690e22081ca8f99544.tar.gz
qemu-5ef84f111483e3f7b57efc690e22081ca8f99544.tar.xz
qemu-5ef84f111483e3f7b57efc690e22081ca8f99544.zip
target/arm: Implement ARMv8.5-CondM
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/cpu.h')
-rw-r--r--target/arm/cpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index fc2909ea6d..a7aaec63d7 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3436,6 +3436,11 @@ static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
}
+static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
+{
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
+}
+
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;