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| author | Peter Maydell | 2019-04-29 18:36:01 +0200 |
|---|---|---|
| committer | Peter Maydell | 2019-04-29 18:36:01 +0200 |
| commit | 6d60c67a1a03be32c3342aff6604cdc5095088d1 (patch) | |
| tree | 70a9f2bac311ba4d98f16ebf51ec72bd9f91064d /target/arm/cpu.h | |
| parent | target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags (diff) | |
| download | qemu-6d60c67a1a03be32c3342aff6604cdc5095088d1.tar.gz qemu-6d60c67a1a03be32c3342aff6604cdc5095088d1.tar.xz qemu-6d60c67a1a03be32c3342aff6604cdc5095088d1.zip | |
target/arm: Set FPCCR.S when executing M-profile floating point insns
The M-profile FPCCR.S bit indicates the security status of
the floating point context. In the pseudocode ExecuteFPCheck()
function it is unconditionally set to match the current
security state whenever a floating point instruction is
executed.
Implement this by adding a new TB flag which tracks whether
FPCCR.S is different from the current security state, so
that we only need to emit the code to update it in the
less-common case when it is not already set correctly.
Note that we will add the handling for the other work done
by ExecuteFPCheck() in later commits.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-19-peter.maydell@linaro.org
Diffstat (limited to 'target/arm/cpu.h')
| -rw-r--r-- | target/arm/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 99ccb4824d..a2cf9aae3a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3153,6 +3153,8 @@ FIELD(TBFLAG_A32, NS, 6, 1) FIELD(TBFLAG_A32, VFPEN, 7, 1) FIELD(TBFLAG_A32, CONDEXEC, 8, 8) FIELD(TBFLAG_A32, SCTLR_B, 16, 1) +/* For M profile only, set if FPCCR.S does not match current security state */ +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) /* For M profile only, Handler (ie not Thread) mode */ FIELD(TBFLAG_A32, HANDLER, 21, 1) /* For M profile only, whether we should generate stack-limit checks */ |